The present invention relates to the configurations of the source and drain regions of a MOS transistor forming a part of a semiconductor integrated circuit device and, more particularly, to a manufacturing method for determining the impurity density at boundaries between the channel region and the source and drain regions.
In order to prevent the deterioration of the characteristics of MOS transistors having a small channel length due to hot carriers, which has arisen as MOS transistors have become finer, it has become common to employ an LDD structure having low-density diffusion layer regions in the vicinity of the edges of the gate electrode, i.e., in the vicinity of the boundaries between the channel region and the source and drain regions to relax a high electric field in the vicinity of the drain edge.
FIG. 7 is a schematic sectional view illustrating a process of forming source and drain diffusion layer regions of a conventional LDD type MOS transistor.
Impurities are introduced using first impurity ion beams 702 to form low-density diffusion layers of a second conductivity type in regions on a semiconductor substrate of a first conductivity type which have been selected using a patterned resist 701.
At this time, since a thick silicon oxide film 707 and a gate electrode 705 made of polysilicon or the like serve as a mask to select the regions into which impurities are to be introduced in the same manner as the resist 701, the impurities are introduced only to regions 703 under a thin silicon oxide film 708 which are not covered by the gate electrode and the resist (FIG. 7A).
Next, after forming a silicon oxide film layer 704 on the entire surface by means of deposition using CVD or the like (FIG. 7B), anisotropic etching is performed on the silicon oxide film layer 704 to form side walls 706 constituted by silicon oxide films on the gate electrode 705 (FIG. 7C).
Thereafter, impurities are introduced again but, this time, using second impurity ion beams 709 to form high-density diffusion layers 710 of the second conductivity type in regions selected using a patterned resist 711 and, further, thermal diffusion is performed.
Then, the regions directly under the silicon oxide film side walls 706 become low-density diffusion layers 703 and the rest of the source and drain regions become high-density diffusion layers 710 (FIG. 7D).
When a conventional MOS transistor having an LDD structure is formed, as shown in FIG. 6, a pattern 602 as an impurity introduction mask for selecting regions into which impurities for forming low-density impurity layers and high-density impurity layers are introduced, is drawn to cover the entire surface of a source region 603, a drain region 604, and a channel region directly under a gate electrode 601 which generally serve as an active region.
It is widely known that such an LDD structure allows a MOS transistor to have higher resistance to hot carriers.
However, the cost of a conventional LDD type MOS transistor could be increased by complicated processes involved such as the two impurity introduction processes and the process of forming the silicon oxide film side walls as described above.
Further, although an LDD type MOS transistor has excellent resistance to hot carriers, it is vulnerable to surge stresses such as external static electricity, and a conventional (non-LDD) type transistor whose source and drain regions are constituted only by high-density diffusion layers is better with respect to resistance to breakage due to static electricity. As a result, semiconductor integrated circuit devices have been sometimes manufactured by adding a process for fabricating conventional (non-LDD) type MOS transistors having a relatively large channel length to be used as an input protection circuit and an output transistor instead of those having the LDD structure.